--- linux-2.6.23/drivers/acpi/Makefile 2007-07-23 21:34:08.000000000 +0200 +++ linux-2.6.23-jo/drivers/acpi/Makefile 2007-11-01 17:06:33.000000000 +0100 @@ -60,3 +60,8 @@ obj-$(CONFIG_ACPI_HOTPLUG_MEMORY) += acpi_memhotplug.o obj-y += cm_sbs.o obj-$(CONFIG_ACPI_SBS) += sbs.o +# +# not really ACPI thing, but closely related +# +obj-$(CONFIG_AMD76X_PM) += amd76x_pm.o + --- linux-2.6.23/drivers/acpi/Kconfig 2007-10-30 20:12:19.000000000 +0100 +++ linux-2.6.23-jo/drivers/acpi/Kconfig 2007-11-01 17:07:09.000000000 +0100 @@ -358,3 +358,18 @@ to today's ACPI "Control Method" battery. endif # ACPI + +config AMD76X_PM + tristate "AMD76x Native Power Management support" + default n + depends on X86 && PCI + help + This driver enables Power Management on AMD760MP & AMD760MPX + chipsets. This is about same as ACPI C3, but ACPI doesn't + support known AMD760MP(X) boards. + See Documentation/amd76x_pm.txt for details. + + Say M here to build a module called amd76x_pm. + + If unsure, say N. + --- linux-2.6.23/drivers/acpi/amd76x_pm.c 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.23-jo/drivers/acpi/amd76x_pm.c 2007-11-01 17:06:33.000000000 +0100 @@ -0,0 +1,764 @@ +/* + * ACPI style PM for SMP AMD-760MP(X) based systems. + * + * Copyright (C) 2002 Johnathan Hicks + * Tony Lindgren + * + * Copyright (C) 2005-2006 Joerg Sommrey + * + * See Documentation/amd76x_pm.txt for details. + * + * This software is licensed under GNU General Public License Version 2 + * as specified in file COPYING in the Linux kernel source tree main + * directory. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define VERSION "20070724" + +//#define AMD76X_LOG_C1 1 + +static void amd76x_smp_idle(void); +static int amd76x_pm_main(void); + +static unsigned long lazy_idle __read_mostly; +static unsigned long spin_idle __read_mostly; +static unsigned long watch_int; +static unsigned long min_C1 = AMD76X_MIN_C1; +static unsigned int sb_id; +static unsigned int nb_id; +static int mode __read_mostly = AMD76X_MODE; +static int watch_irqs[AMD76X_WATCH_MAX]; +static int nr_watch_irqs; +static int watch_limits[AMD76X_WATCH_MAX]; +static int nr_watch_limits; +static int irq_count[AMD76X_WATCH_MAX]; +static int stats __read_mostly = 0; + +module_param(lazy_idle, long, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(lazy_idle, + " number of idle cycles before entering power saving mode"); + +module_param(spin_idle, long, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(spin_idle, + " number of spin cycles to wait for other CPUs to become idle"); + +module_param(watch_int, long, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(watch_int, + " watch interval (in milliseconds) for interrupts"); + +module_param(mode, int, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(mode, " idling mode"); + +module_param_array(watch_irqs, int, &nr_watch_irqs, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(watch_irqs, + " list of irqs to be watched"); + +module_param_array(watch_limits, int, &nr_watch_limits, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(watch_limits, + " interrupt rate that causes fallback to C1 idling if" + " corresponding interrupt exceeds this rate"); + +module_param(min_C1, long, S_IRUGO | S_IWUSR); +MODULE_PARM_DESC(min_C1, + " minimum irq rate watch intervals spent in C1 mode"); + +module_param(stats, bool, S_IRUGO); +MODULE_PARM_DESC(stats, + " generate sleep rate stats"); + +MODULE_AUTHOR("Tony Lindgren, Johnathan Hicks, Joerg Sommrey, others"); +MODULE_DESCRIPTION("ACPI style power management for SMP AMD-760MP(X) " + "based systems, version " VERSION); + + +static struct pci_dev *pdev_nb; +static struct pci_dev *pdev_sb; + +struct PM_cfg { + void (*orig_idle) (void); + void (*curr_idle) (void); +}; + +static struct PM_cfg amd76x_pm_cfg; + +struct PM_slp { + unsigned int C2_reg; + unsigned int C3_reg; + unsigned int status_reg; + unsigned int tmr_reg; +}; + +static struct PM_slp amd76x_pm_slp __read_mostly; + +struct cpu_stat { + int idle_count; + int sleep_cnt; + unsigned long last; + long sleep_rate; +}; + +struct idle_stat { + atomic_t num_idle; +}; + +static struct idle_stat amd76x_stat __cacheline_aligned_in_smp = { + .num_idle = ATOMIC_INIT(0), +}; + +static void *prs_ref __read_mostly; + +/* save register contents + */ +struct reg_save { + unsigned int nb58; + unsigned int nb60; + unsigned int nb68; + unsigned int nb70; + unsigned int sb41; + unsigned int sb4f; + unsigned int sb50; +}; + +static struct reg_save amd76x_saved; + +static int force_C1 __read_mostly; + +static void watch_irq(struct work_struct *); + +static DECLARE_DELAYED_WORK(work_item, &watch_irq); + +static struct pci_device_id __devinitdata amd_nb_tbl[] = { + {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, PCI_ANY_ID, + PCI_ANY_ID,}, + {0,} +}; + +static struct pci_device_id __devinitdata amd_sb_tbl[] = { + {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7413, PCI_ANY_ID, + PCI_ANY_ID,}, + {PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7443, PCI_ANY_ID, + PCI_ANY_ID,}, + {0,} +}; + +/* + * Configures the AMD-762 northbridge to support PM calls + */ +static int config_amd762(int enable) +{ + unsigned int regdword; + + /* Enable/disable STPGNT in BIU Status/Control for cpu0, + * page 64 in AMD-762 doc */ + pci_read_config_dword(pdev_nb, 0x60, ®dword); + if (enable) + amd76x_bits_set_store(amd76x_saved.nb60, -1, + STP_GRANT_DISCON_EN, regdword); + else + amd76x_bits_restore(amd76x_saved.nb60, + STP_GRANT_DISCON_EN, regdword); + pci_write_config_dword(pdev_nb, 0x60, regdword); + + /* Enable/disable STPGNT in BIU Status/Control for cpu1, + * page 69 in AMD-762 doc */ + pci_read_config_dword(pdev_nb, 0x68, ®dword); + if (enable) + amd76x_bits_set_store(amd76x_saved.nb68, -1, + STP_GRANT_DISCON_EN, regdword); + else + amd76x_bits_restore(amd76x_saved.nb68, + STP_GRANT_DISCON_EN, regdword); + pci_write_config_dword(pdev_nb, 0x68, regdword); + + /* dis/enable "DRAM refresh disable", page 60 in AMD-762 doc */ + pci_read_config_dword(pdev_nb, 0x58, ®dword); + if (enable) + amd76x_bits_set_store(amd76x_saved.nb58, 0, + REF_DIS, regdword); + else + amd76x_bits_restore(amd76x_saved.nb58, + REF_DIS, regdword); + pci_write_config_dword(pdev_nb, 0x58, regdword); + + /* Self refresh enable, page 75 in AMD-762 doc */ + pci_read_config_dword(pdev_nb, 0x70, ®dword); + if (enable) + amd76x_bits_set_store(amd76x_saved.nb70, -1, + SELF_REF_EN, regdword); + else + amd76x_bits_restore(amd76x_saved.nb70, + SELF_REF_EN, regdword); + pci_write_config_dword(pdev_nb, 0x70, regdword); + + return 0; +} + + +/* + * Get the base PMIO address and set the pm registers in amd76x_pm_cfg. + */ +static void amd76x_get_PM(void) +{ + unsigned int regdword; + + /* Get the address for pm status, P_LVL2, etc + * DevB:3x58, page 102 in AMD-768 doc + * C3A58, page 64 in AMD-766 doc + */ + pci_read_config_dword(pdev_sb, 0x58, ®dword); + regdword &= PMBASE; + amd76x_pm_slp.status_reg = (regdword + 0x00); + amd76x_pm_slp.tmr_reg = (regdword + 0x08); + amd76x_pm_slp.C2_reg = (regdword + 0x14); + amd76x_pm_slp.C3_reg = (regdword + 0x15); +} + +/* + * En/Disable PMIO and configure W4SG & STPGNT. + */ +static int config_PMIO_amd76x(int is_766, int enable) +{ + unsigned char regbyte; + unsigned char bits = 0; + + /* Set W4SG and PMIOEN, if using a 765/766 set STPGNT as well. + * AMD-766: C3A41; page 59 in AMD-766 doc + * AMD-768: DevB:3x41; page 94 in AMD-768 doc */ + pci_read_config_byte(pdev_sb, 0x41, ®byte); + if (is_766) + bits |= STPGNT; + bits |= (PMIOEN | W4SG | TMR32); + if (enable) + amd76x_bits_set_store(amd76x_saved.sb41, + -1, bits, regbyte); + else + amd76x_bits_restore(amd76x_saved.sb41, + bits, regbyte); + pci_write_config_byte(pdev_sb, 0x41, regbyte); + return 0; +} + +/* + * C2/C3 idle support for AMD-766. + */ +static void config_amd766_Cx(int enable) +{ + unsigned int regdword; + + /* Set C2/C3 options in C3A50, page 63 in AMD-766 doc */ + pci_read_config_dword(pdev_sb, 0x50, ®dword); + if (enable) { + amd76x_bits_set_store(amd76x_saved.sb50, + ((STPCLK_EN | CPUSLP_EN) << C2_REGS) | + ((STPCLK_EN | CPUSLP_EN | CPUSTP_EN) << C3_REGS), + ((DCSTOP_EN | PCISTP_EN | SUSPND_EN | CPURST_EN | + STPCLK_EN | CPUSLP_EN) << C2_REGS) | + ((DCSTOP_EN | PCISTP_EN | SUSPND_EN | CPURST_EN | + STPCLK_EN | CPUSLP_EN | CPUSTP_EN) << C3_REGS), + regdword); + } else + amd76x_bits_restore(amd76x_saved.sb50, + ((DCSTOP_EN | PCISTP_EN | SUSPND_EN | CPURST_EN | + STPCLK_EN | CPUSLP_EN) << C2_REGS) | + ((DCSTOP_EN | PCISTP_EN | SUSPND_EN | CPURST_EN | + STPCLK_EN | CPUSLP_EN | CPUSTP_EN) << C3_REGS), + regdword); + pci_write_config_dword(pdev_sb, 0x50, regdword); +} + +/* + * Configures the 765 & 766 southbridges. + */ +static int config_amd766(int enable) +{ + if (enable) + amd76x_get_PM(); + config_PMIO_amd76x(1, enable); + config_amd766_Cx(enable); + return 0; +} + +/* + * C2/C3 idling support for AMD-768. + */ +static void config_amd768_Cx(int enable) +{ + unsigned char regbyte; + + /* Set C2/C3 options in DevB:3x4F, page 100 in AMD-768 doc */ + pci_read_config_byte(pdev_sb, 0x4F, ®byte); + if (enable) + amd76x_bits_set_store(amd76x_saved.sb4f, -1, + C2EN | C3EN | ZZ_C3EN | CSLP_C3EN | CSTP_C3EN, + regbyte); + else + amd76x_bits_restore(amd76x_saved.sb4f, + C2EN | C3EN | ZZ_C3EN | CSLP_C3EN | CSTP_C3EN, + regbyte); + pci_write_config_byte(pdev_sb, 0x4F, regbyte); +} + +/* + * Configures the 768 southbridge to support idle calls, and gets + * the processor idle call register location. + */ +static int config_amd768(int enable) +{ + if (enable) + amd76x_get_PM(); + config_PMIO_amd76x(0, enable); + config_amd768_Cx(enable); + return 0; +} + +/* + * Idle loop for single processor systems + */ +void amd76x_up_idle(void) +{ + /* ACPI knows how to do C2/C3 on SMP when cpu_count < 2 + * we really shouldn't end up here anyway. + */ + amd76x_pm_cfg.orig_idle(); +} + +/* + * Idle loop for SMP systems + * + */ +static void amd76x_smp_idle(void) +{ + int i; + int num_online; + struct cpu_stat *prs; + unsigned long newticks; + unsigned long oldticks = 0; + long cycleticks; + long sleepticks; + s64 tmp; + int posval; + int cpu; + + if (unlikely(force_C1)) { + local_irq_disable(); + safe_halt(); + return; + } + + cpu = raw_smp_processor_id(); + prs = per_cpu_ptr(prs_ref, cpu); + /* Spin inside (outer) idle loop until lazy_idle cycles + * are reached. + */ + if (likely(++(prs->idle_count) <= lazy_idle)) + return; + + /* Now we are ready do go C2/C3. */ + num_online = num_online_cpus(); + prs->idle_count = 0; + + smp_mb__before_atomic_inc(); + atomic_inc(&amd76x_stat.num_idle); + + /* quote from processor_idle.c: + * TS_POLLING-cleared state must be visible before we + * test NEED_RESCHED + */ + current_thread_info()->status &= ~TS_POLLING; + + /* Spin inside inner loop until either + * - spin_idle cycles are reached + * - there is scheduled work + * - all CPUs are idle + */ + for (i = 0; i < spin_idle && !need_resched(); i++) { + smp_mb(); + if (unlikely(atomic_read(&amd76x_stat.num_idle) + == num_online)) + goto sleepy; + cpu_relax(); + } + current_thread_info()->status |= TS_POLLING; + + smp_mb__before_atomic_dec(); + atomic_dec(&amd76x_stat.num_idle); + return; + +sleepy: + current_thread_info()->status |= TS_POLLING; + local_irq_disable(); + prs->sleep_cnt++; + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu); + if (unlikely(stats)) + oldticks = inl(amd76x_pm_slp.tmr_reg); + /* Invoke C2/C3 */ + switch (mode) { + case 2: + inb(amd76x_pm_slp.C2_reg); + break; + case 3: + acpi_set_register(ACPI_BITREG_ARB_DISABLE, 1); + inb(amd76x_pm_slp.C3_reg); + break; + } + /* quote from processor_idle.c: + * Dummy wait op - must do something useless after P_LVL2 read + * because chipsets cannot guarantee that STPCLK# signal + * gets asserted in time to freeze execution properly. + */ + newticks = inl(amd76x_pm_slp.tmr_reg); + acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0); + if (unlikely(stats)) + newticks = inl(amd76x_pm_slp.tmr_reg); + smp_mb__before_atomic_dec(); + atomic_dec(&amd76x_stat.num_idle); + mark_tsc_unstable("possible TSC halt in Cx sleep state"); + local_irq_enable(); + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu); + + /* average sleep rate + * unit: percent * AVG_SCALE + * (AVG_SCALE is needed for integer arithmetics) + * cycle_time: time since last idle call + * sleep_time: time spent in C2/C3 + * sleep_rate = 100 * AVG_SCALE * sleep_time / cycle_time + * general formula: + * avg_sleep_rate = + * ((AVG_WIN - cycle_time) * avg_sleep_rate + + * cycle_time * sleep_rate) / AVG_WIN + */ + + if (likely(!stats)) + return; + + cycleticks = newticks - prs->last; + sleepticks = newticks - oldticks; + + tmp = 100 * AVG_SCALE * (s64) sleepticks - + (s64) cycleticks * prs->sleep_rate; + posval = (tmp >= 0) ? 1 : 0; + if (!posval) tmp = -tmp; + do_div(tmp, AVG_WIN * PM_TMR_FREQ); + + prs->sleep_rate = prs->sleep_rate + (posval ? tmp : -tmp); + prs->last = newticks; + return; +} + +/* + * sysfs support, RW + */ +static ssize_t show_sleep_cnt (struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct cpu_stat *prs; + ssize_t ret = 0; + int cpu; + + for_each_online_cpu(cpu) { + prs = per_cpu_ptr(prs_ref, cpu); + ret += sprintf(buf + ret, "%u ", prs->sleep_cnt); + } + buf[ret - 1] = '\n'; + return ret; +} + +static DEVICE_ATTR(sleep_cnt, S_IRUGO, + show_sleep_cnt, NULL); + +static ssize_t show_sleep_rate (struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct cpu_stat *prs; + ssize_t ret = 0; + int cpu; + unsigned long sleep_cnt; + + /* If processors are busy, sleep_rate will not be updated and is + * therefore invalid/meaningless. + * Pick any CPU, wait a few clock ticks and see if the CPU has been + * sleeping. + */ + cpu = raw_smp_processor_id(); + prs = per_cpu_ptr(prs_ref, cpu); + sleep_cnt = prs->sleep_cnt; + schedule_timeout_uninterruptible(SLEEP_RATE_WAIT); + if (prs->sleep_cnt == sleep_cnt) + return sprintf(buf, "0 0\n"); + + for_each_online_cpu(cpu) { + prs = per_cpu_ptr(prs_ref, cpu); + ret += sprintf(buf + ret, "%ld ", + prs->sleep_rate / AVG_SCALE); + } + buf[ret - 1] = '\n'; + return ret; +} + +static DEVICE_ATTR(sleep_rate, S_IRUGO, + show_sleep_rate, NULL); + +/* setup the irq watcher task */ +static void setup_watch(void) +{ + if (watch_int <= 0) + watch_int = AMD76X_WATCH_INT; + if (min(nr_watch_irqs, nr_watch_limits) > 0 && watch_int > 0) { + schedule_delayed_work(&work_item, 0); + printk(KERN_INFO "amd76x_pm: irq rate watcher started. " + "watch_int = %lu ms, min_C1 = %lu\n", + watch_int, min_C1); + } else { + nr_watch_irqs = 0; + nr_watch_limits = 0; + watch_int = 0; + printk(KERN_INFO "amd76x_pm: irq rate watcher disabled.\n"); + } +} + +/* watch the irq rate of configured irqs and force C1 if rate is above + * given limit. This function is scheduled via the work queue and will + * schedule itself until disabled. + */ +static void watch_irq(struct work_struct *work) +{ + int i; + int irq_cnt; + int set_force_C1 = 0; + + for (i = 0; i < min(nr_watch_irqs, nr_watch_limits); i++) { + irq_cnt = kstat_irqs(watch_irqs[i]); + if ((irq_cnt - irq_count[i]) * 1000 > + watch_limits[i] * watch_int) { + set_force_C1 = 1; + } + irq_count[i] = irq_cnt; + } + +#ifdef AMD76X_LOG_C1 + if (set_force_C1 && !force_C1) + printk(KERN_INFO "amd76x_pm: C1 on\n"); + if (!set_force_C1 && force_C1 == 1) + printk(KERN_INFO "amd76x_pm: C1 off\n"); +#endif + + if (set_force_C1) + force_C1 = min_C1; + else if (force_C1) + force_C1--; + + if (watch_int > 0 && min(nr_watch_irqs, nr_watch_limits) > 0) + schedule_delayed_work(&work_item, + msecs_to_jiffies(watch_int)); + else { + nr_watch_irqs = 0; + nr_watch_limits = 0; + watch_int = 0; + force_C1 = 0; + printk(KERN_INFO "amd76x_pm: irq rate watcher stopped.\n"); + } +} + + +/* + * Finds and initializes the bridges, and then sets the idle function + */ +static int amd76x_pm_main(void) +{ + int cpu; + struct cpu_stat *prs; + int rc; + + if (mode != 2 && mode != 3) + return -EINVAL; + + amd76x_pm_cfg.orig_idle = 0; + if(lazy_idle == 0) + lazy_idle = AMD76X_LAZY_IDLE; + printk(KERN_INFO "amd76x_pm: lazy_idle = %lu\n", lazy_idle); + if(spin_idle == 0) + spin_idle = 2 * lazy_idle; + printk(KERN_INFO "amd76x_pm: spin_idle = %lu\n", spin_idle); + printk(KERN_INFO "amd76x_pm: using C%d idling\n", mode); + + /* Find southbridge */ + for_each_pci_dev(pdev_sb) + if(pci_match_id(amd_sb_tbl, pdev_sb) != NULL) + goto found_sb; + + printk(KERN_ERR "amd76x_pm: Could not find southbridge\n"); + return -ENODEV; + +found_sb: + /* Find northbridge */ + for_each_pci_dev(pdev_nb) + if(pci_match_id(amd_nb_tbl, pdev_nb) != NULL) + goto found_nb; + printk(KERN_ERR "amd76x_pm: Could not find northbridge\n"); + return -ENODEV; + +found_nb: + + /* Init southbridge */ + switch (pdev_sb->device) { + case PCI_DEVICE_ID_AMD_VIPER_7413: /* AMD-765 or 766 */ + sb_id = PCI_DEVICE_ID_AMD_VIPER_7413; + config_amd766(1); + break; + case PCI_DEVICE_ID_AMD_VIPER_7443: /* AMD-768 */ + sb_id = PCI_DEVICE_ID_AMD_VIPER_7443; + config_amd768(1); + break; + default: + printk(KERN_ERR "amd76x_pm: No southbridge to initialize\n"); + break; + } + + /* Init northbridge and queue the new idle function */ + if(!pdev_nb) { + printk("amd76x_pm: No northbridge found.\n"); + return -ENODEV; + } + + switch (pdev_nb->device) { + case PCI_DEVICE_ID_AMD_FE_GATE_700C: /* AMD-762 */ + nb_id = PCI_DEVICE_ID_AMD_FE_GATE_700C; + config_amd762(1); + amd76x_pm_cfg.curr_idle = amd76x_smp_idle; + break; + default: + printk(KERN_ERR "amd76x_pm: No northbridge to initialize\n"); + break; + } + + if(num_online_cpus() == 1) { + amd76x_pm_cfg.curr_idle = amd76x_up_idle; + printk(KERN_ERR "amd76x_pm: UP machine detected. " + "ACPI is your friend.\n"); + } + if (!amd76x_pm_cfg.curr_idle) { + printk(KERN_ERR "amd76x_pm: Idle function not changed\n"); + return 1; + } + + prs_ref = alloc_percpu(struct cpu_stat); + + for_each_possible_cpu(cpu) { + prs = per_cpu_ptr(prs_ref, cpu); + prs->idle_count = 0; + prs->sleep_cnt = 0; + prs->sleep_rate = 0; + prs->last = 0; + clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ON, &cpu); + } + + amd76x_pm_cfg.orig_idle = pm_idle; + pm_idle = amd76x_pm_cfg.curr_idle; + + wmb(); + + /* sysfs */ + rc = device_create_file(&pdev_nb->dev, &dev_attr_sleep_cnt); + if (stats) + rc = device_create_file(&pdev_nb->dev, &dev_attr_sleep_rate); + + setup_watch(); + + return 0; +} + + +static int __init amd76x_pm_init(void) +{ + int ret; + ret = amd76x_pm_main(); + if (ret == 0) + printk(KERN_INFO "amd76x_pm: Version %s loaded.\n", VERSION); + else + printk(KERN_INFO "amd76x_pm: Version %s loading failed.\n", + VERSION); + + return ret; +} + + +static void __exit amd76x_pm_cleanup(void) +{ + int cpu; + unsigned int sleep_cnt = 0; + struct cpu_stat *prs; + + pm_idle = amd76x_pm_cfg.orig_idle; + + cpu_idle_wait(); + + /* This isn't really needed. */ + for_each_online_cpu(cpu) { + prs = per_cpu_ptr(prs_ref, cpu); + sleep_cnt += prs->sleep_cnt; + } + printk(KERN_INFO "amd76x_pm: %u C2/C3 calls\n", + sleep_cnt); + + /* remove sysfs */ + device_remove_file(&pdev_nb->dev, &dev_attr_sleep_cnt); + if (stats) + device_remove_file(&pdev_nb->dev, &dev_attr_sleep_rate); + + /* disable the irq rate watcher */ + watch_int = 0; + flush_scheduled_work(); + cancel_delayed_work(&work_item); + flush_scheduled_work(); + + /* free percpu memory */ + free_percpu(prs_ref); + + switch (sb_id) { + case PCI_DEVICE_ID_AMD_VIPER_7413: /* AMD-765 or 766 */ + config_amd766(0); + break; + case PCI_DEVICE_ID_AMD_VIPER_7443: /* AMD-768 */ + config_amd768(0); + break; + default: + printk(KERN_ERR "amd76x_pm: No southbridge to deinitialize\n"); + break; + } + + switch (nb_id) { + case PCI_DEVICE_ID_AMD_FE_GATE_700C: /* AMD-762 */ + config_amd762(0); + break; + default: + printk(KERN_ERR "amd76x_pm: No northbridge to deinitialize\n"); + break; + } +} + + +MODULE_LICENSE("GPL v2"); +module_init(amd76x_pm_init); +module_exit(amd76x_pm_cleanup); --- linux-2.6.23/Documentation/amd76x_pm.txt 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.23-jo/Documentation/amd76x_pm.txt 2007-11-01 17:06:33.000000000 +0100 @@ -0,0 +1,305 @@ + ACPI style power management for SMP AMD-760MP(X) based systems + ============================================================== + +The ACPI project now supports C3 for SMP. However, to get AMD K7 +into C2/C3 some registers need to be adjusted. This should be done by +the BIOS, but it isn't on known boards. You may read this as: "This +feature is not supported". Because of this, there is no C2/C3 support +from the ACPI processor module and there will be probably none in the +future. + +Using the module is regarded as dangerous. +USE THIS SOFTWARE ON YOUR OWN RISK. + +When this module is loaded and properly parameterised it saves about +70 - 90 W of energy in the idle mode compared to the default idle mode. +Waking up from the idle mode is fast to keep the system response time +good. + +This code runs on two-way AMD boxes at the moment, but the basic idling +algorithm is independent of the number of CPUs. + +Known issues: +============= +- Currently there's a bug somewhere where the reading the + P_LVL2 for the first time causes the system to sleep instead of + idling. This means that you need to hit the power button once to + wake the system after loading the module for the first time after + reboot. After that the system idles as supposed. + (Only observed on Tony's system - S2460.) + +- There might be reduced throughput of disk or network devices. See + below for how to configure the "irq rate watcher" to avoid this. + +- Occasional hard lockups might be caused by amd76x_pm. I've run out of + ideas how to track this problem down a.t.m. + +- I have reports about a buzzing sound from the mainboard when amd76x_pm + is loaded and some reports about unclean audio playback. + +- sleep_rate sometimes shows illegal values right after insmod. Some + nasty integer overflow. + +- C2 mode and the pm-timer don't work well together. Consider using C2 + with tsc or C3 with pm-timer. + +- In recent kernels (2.6.18) there seems to be a problem when using + pm_timer as clock source together with amd76x_pm. Timers and/or timed + waits may be remarkably delayed. + +Influenced by Vcool, and LVCool. Rewrote everything from scratch to +use the PCI features in Linux, and to support SMP systems. (Tony) + +Currently tested amongst others on a TYAN S2460 (760MP) system (Tony), an +ASUS A7M266-D (760MPX) system (Johnathan) and a TYAN S2466 (760MPX) +system (Jo), success reports from TYAN S2462, MSI K7D, ASUS A7M266-D, +Gigabyte GA-7DPXDW+. Adding support for other Athlon SMP or single +processor systems should be easy if desired. + +The file /sys/devices/pci0000:00/0000:00:00.0/sleep_cnt shows the number of +C2/C3 calls (per CPU) since module load. If the module is loaded with +stats=y then you find an average (per CPU) sleep rate over the last few +seconds in /sys/devices/pci0000:00/0000:00:00.0/sleep_rate (measured in +percent). sleep_rate reads as zero if the system is busy for several +clock ticks. + +Consider using amd76x_pm together with a tickless system (NO_HZ) +introduced in 2.6.21 for maximum power saving. + +Parameters +========== +There are some parameters for tuning the behaviour of amd76x_pm: +mode, lazy_idle, spin_idle, watch_irqs, watch_limits, watch_int and min_C1 + +- stats enables the calculation of sleep_rate in + /sys/devices/pci0000:00/0000:00:00.0/. Default: stats=n + +- mode lets you select between C2 and C3 idling. There are two main + differences between C2 and C3 idling: power consumption in C3 is even + lower than in C2 and "cache spoofing" is disabled in C3. This means: + DMA bus mastering activities are still possible in C2 and cause a + wakeup in C3. As this wakeup takes a few cycles you shall expect some + latencies with DMA in C3. Default: mode=3 + +lazy_idle and spin_idle are closely related: + +- lazy_idle defines the number of idle calls into amd76x_smp_idle that are + needed to enter C2/C3 mode. This parameter is the maximum loop + counter for an outer loop. Default: lazy_idle=64 + +- spin_idle defines the maximum number of spin cycles in an inner idle loop + where one CPU waits for all others to become idle. When all CPUs are + idle, C2/C3 state is entered. Default: spin_idle=4*lazy_idle + +lazy_idle and spin_idle define a "rubber measure" for the idling +behaviour: lazy_idle defines the minimum idle cycles needed to enter +C2/C3 and spin_idle defines when to give up. + +Low values for lazy_idle and high values for spin_idle give better +cooling. Higher values for lazy_idle simply give less cooling. + +irq rate watcher: +----------------- +Interrupts are disabled in C2/C3 mode. CPUs are woken up by timer +interrupts or by SMIs/NMIs (and DMA bus mastering in case of C3). This +causes high interrupt latencies for non-timer interrupts that might lead +to a significant reduction in i/o or network throughput. There has been +introduced an "irq rate watcher" to get rid of this issue. If the irq +rate watcher detects that an interrupt has a rate above a given limit, +C2/C3 idling will be disabled and a low latency C1 idling mode is used +instead (HLT instruction). The parameters watch_irqs, watch_limits, +watch_int and min_C1 control this irq rate watcher: + +- watch_irqs defines which interrupts are to be watched. This is a + comma separated list of interrupts. To enable the irq rate watcher + you must specify this parameter. You may provide the interrupts used + by disk controllers or network adapters here. Default: none + +- watch_limits defines at which interrupt rate C2/C3 mode shall be + disabled. This is a list of comma separated interrupt rates per + second. To enable the irq rate watcher you must specify this + parameter. Watch the interrupt rates for those devices you are + interested in and choose a limit that discrimitates idle from busy + state. Default: none + +- watch_int defines the time interval (in milliseconds) at which the + interrupt rate is checked. Too low values may result in an overhead + and too high values cause the C1 mode to kick in later. + Default: watch_int=500 + +- min_C1 defines the mininum number of check intervals with low + interrupt rates that are needed to leave the forced C1 mode. + Default: min_C1=2 + +All parameters may be given as module parameters to amd76x_pm and +queried/altered via their sysfs entries in /sys/module/amd76x_pm/parameters. + +To get the irq watcher started, watch_int, watch_irqs and watch_limits +must all be provided. If any of these parameters is cleared via sysfs, +the irq rate watcher stopps and cannot be restarted (unless the module +is reloaded). + +Some hints on tuning lazy_idle and spin_idle: +Watch sleep_rate in sysfs on an almost idle system. Start with a low +value for lazy_idle and spin_idle, e.g. 8. Raise spin_idle, e.g. by +doubling. This should cause a raise in sleep_rate. Stop when +there's no more change in sleep_rate. Then raise lazy_idle, e.g. by +doubling. If this causes a sleep_rate reduction, try to raise +spin_idle. Stop raising lazy_idle when you cannot compensate the sleep +rate reduction with a spin_idle raise. (You may use this as a starting +point for furter fine tuning.) + +Further notes +============= +There are complex dependencies between several settings: +- HZ +- preemption model +- time source (tsc, pmtmr,...) +- mode (C2/C3) +- probably others + +If you want to do further experiments this field: There is another +version of amd76x_pm.c that has experimental und untested support for +"normal throttling" and "power on suspend". See +http://www.sommrey.de/amd76x_pm + +License +======= +This software is licensed under GNU General Public License Version 2 +as specified in file COPYING in the Linux kernel source tree main +directory. + +Copyright (C) 2002 Johnathan Hicks + Tony Lindgren + +Copyright (C) 2005 - 2007 Joerg Sommrey + +History +======= + + 20020702 - amd-smp-idle: Tony Lindgren +Influenced by Vcool, and LVCool. Rewrote everything from scratch to +use the PCI features in Linux, and to support SMP systems. Provides +C2 idling on SMP AMD-760MP systems. + + 20020722: JH + I adapted Tony's code for the AMD-765/766 southbridge and adapted it + according to the AMD-768 data sheet to provide the same capability for + SMP AMD-760MPX systems. Posted to acpi-devel list. + + 20020722: Alan Cox + Replaces non-functional amd76x_pm code in -ac tree. + + 20020730: JH + Added ability to do normal throttling (the non-thermal kind), C3 idling + and Power On Suspend (S1 sleep). It would be very easy to tie swsusp + into activate_amd76x_SLP(). C3 idling doesn't happen yet; see my note + in amd76x_smp_idle(). I've noticed that when NTH and idling are both + enabled, my hardware locks and requires a hard reset, so I have + #ifndefed around the idle loop setting to prevent this. POS locks it up + too, both ought to be fixable. I've also noticed that idling and NTH + make some interference that is picked up by the onboard sound chip on + my ASUS A7M266-D motherboard. + + 20030601: Pasi Savolainen + Simple port to 2.5 + Added sysfs interface for making nice graphs with mrtg. + Look for /sys/devices/pci0/00:00.0/C2_cnt & lazy_idle (latter writable) + + 20050601: Joerg Sommrey (jo) + 2.6 stuff + redesigned amd76x_smp_idle. The algorithm is basically the same + but the implementation has changed. This part is now independent + from the number of CPUs and data is locked against concurrent + updates from different CPUs. + use _smp_processor_id() + use cpu_idle_wait() + NTH and POS code not touched and not tested. + + 20050621: jo + separated C3, NTH and POS code into extra patch + + 20050812: jo + rewritten amd76x_smp_idle completely. It's much simpler now but + does a good job - the KISS approach. Introduced a new tunable + spin_idle. + + 20050819: jo + new irq rate watcher task that forces C1-idling if irq-rate exceeds a + given limit. + + 20050820: jo + make all modules parameters r/w in sysfs. + + 20050906: jo + avoid some local_irq_disable/enable + + 20060108: jo + using percpu-variables + + 20060110: jo + eliminated a race condition in the idle loop. Thanks to Arjan van + de Ven, who pointed to this issue. + + 20060121: jo + Switched from C2 to C3 idling, inspired by processor_idle.c + C2 idling has just been replaced by C3 idling, there is no C2/C3 + transition. + Restoring all touched northbridge and southbridge register bits to + their original values on module unload. + + 20060129: jo + Major redesign of the idle loop again. Now there is a two-phase + process to make sure all or no CPUs go into C3. In phase one each + CPU waits for the other to become idle. In phase two all CPUs come + to an agreement about going C3 or not. Now using spinlocks. + Simplicity has gone :-( + + 20060202: jo + Make the source conforming to the kernel coding style. Remove some + minor buglets. + + 20060206: jo + Code redesign for PCI register setup + C2/C3 mode selection + + 20060214: jo + - Redesigned the idle function again. Now there shouldn't be any + situations left where not all CPUs try to enter C2/C3. + - Removed the (ugly) parsing of watch_irqs. Using two separate arrays + watch_irqs and watch_limits now. + - sleep_time calculation and sysfs entries added. + + 20060409: jo + - removed sleep_time in favour of sleep_rate + - mode parameter syntax changed. now: mode={2|3} was: mode={C2|C3} + - mode changeable at runtime + + 20060624: jo + - some changes concerning memory barriers + + 20060719: jo + - removed some double-locking + - code lifting + + 20061010: jo + - trivial 2.6.18 port + + 20061210: jo + - trivial 2.6.19 port + + 20070209: jo + - workqueue API changes in 2.6.20 + + 20070406: jo + - sleep_rate calculation using 64bit arithmetics + + 20070526: jo + - removed "synchronized sleep", i.e. one CPU might enter Cx state if + all other CPUs are idle but not nessecarily entering Cx state. + - run "inner loop" with interrupts enabled + - adopted some system clock related functionalities from + processor_idle.c + + 20070724: jo + - 2.6.22 port --- linux-2.6.23/include/linux/amd76x_pm.h 1970-01-01 01:00:00.000000000 +0100 +++ linux-2.6.23-jo/include/linux/amd76x_pm.h 2007-11-01 17:06:33.000000000 +0100 @@ -0,0 +1,102 @@ +#ifndef __LINUX_AMD76X_PM_H +#define __LINUX_AMD76X_PM_H + +/* + * Begin 762 + */ + +/* BIU0 options in Dev0:F0:0x60, page 64 in AMD-762 doc + * BIU1 options in Dev0:F0:0x68, page 69 in AMD-762 doc + */ +#define STP_GRANT_DISCON_EN (1 << 17) + +/* DRAM control in Dev0:F0:0x58, page 60 in AMD-762 doc */ +#define REF_DIS (1 << 19) + +/* Memory control in Dev0:F0:0x70, page 75 in AMD-762 doc */ +#define SELF_REF_EN (1 << 18) + +/* + * End 762 + */ + +/* + * Begin 765/766 + */ +/* C2/C3 options in C3A50, page 63 in AMD-766 doc */ +#define ZZ_CACHE_EN 1 +#define DCSTOP_EN (1 << 1) +#define STPCLK_EN (1 << 2) +#define CPUSTP_EN (1 << 3) +#define PCISTP_EN (1 << 4) +#define CPUSLP_EN (1 << 5) +#define SUSPND_EN (1 << 6) +#define CPURST_EN (1 << 7) + +#define C2_REGS 0 +#define C3_REGS 8 +/* + * End 765/766 + */ + +/* + * Begin 768 + */ +/* C2/C3 options in DevB:3x4F, page 100 in AMD-768 doc */ +#define C2EN 1 +#define C3EN (1 << 1) +#define ZZ_C3EN (1 << 2) +#define CSLP_C3EN (1 << 3) +#define CSTP_C3EN (1 << 4) +/* + * End 768 + */ + +/* General options in C3A41, page 59 in AMD-766 doc + * devB:3x41, page 94 in AMD-768 doc + */ +#define PMIOEN (1 << 7) +#define W4SG (1 << 0) +#define TMR32 (1 << 3) +#define STPGNT (1 << 1) + +/* PMxx System Management IO Space Pointer + * page 64 in AMD-766 doc + * page 102 in AMD-768 doc + */ +#define PMBASE 0xff80 + +/* parameter defaults */ +#define AMD76X_MODE 3 +#define AMD76X_LAZY_IDLE 1024 +#define AMD76X_WATCH_INT 500 +#define AMD76X_WATCH_LIM 128 +#define AMD76X_WATCH_MAX 8 +#define AMD76X_MIN_C1 2 + +/* timer related stuff */ +/* pm timer frequency */ +#define PM_TMR_FREQ 3579545L +/* window for calculating a sleep tick average */ +#define AVG_WIN 7L +/* need to scale sleep rate when calculating an average: + * make scale large enough to ensure usable results from integer + * division and small enough to avoid integer overflows. + */ +#define AVG_SCALE (((LONG_MAX / PM_TMR_FREQ) * HZ) / 100) + +/* number of time ticks to wait when showing sleep_rate */ +#define SLEEP_RATE_WAIT 8 + +/* some macros for register fiddling */ +/* save + set bits */ +#define amd76x_bits_set_store(save, val, mask, reg) do {\ + save &= ~(mask); save |= (reg) & (mask);\ + reg &= ~(mask); reg |= (mask) & (val);} while(0) + +/* restore bits */ +#define amd76x_bits_restore(save, mask, reg) do {\ + reg &= ~(mask);\ + reg |= (mask) & (save);} while (0) + +#endif